//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //
// Special Function Register Switch for M8051W/EW
// 
// $Log: m3s007dy.v,v $
// Revision 1.4  2001/11/20
// First checkin of version 2 features and name change
//
// Revision 1.2  2001/10/31
// First parsable verilog for EW
//
// Revision 1.1.1.1  2001/07/17
// Re-imported E-Warp from Farnham filesystem
//
// Revision 1.3  2000/10/24
// Multiplier rewritten to improve power consumption.
// Code changes for Leonardo (ECN01372).
// Code changes for formal verification tools (ECN01410).
// MOVX @Ri page address controllable from PORT2I if I/O ports ommitted (ECN01387).
//
// Revision 1.2  2000/02/05
// Name change repercussions
//
// Revision 1.1.1.1  1999/10/28
// "initialization and source check-in for m8051e"
//
// Revision 1.1  1999/10/22
// Initial revision
//
////////////////////////////////////////////////////////////////////////////////

`include "m8051w_defs.v"

module m3s007dy (SFR_DATA, SFR_WRITE_EN, SOURCE_ADDR, DESTIN_ADDR, SFR_WRITE,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //
                 STACK_POINTER, PSW, ACC, B, PCON, DPTR_SFR_DATA, INTR_SFR_DATA,
                 PORTS_SFR_DATA, TIMER_SFR_DATA, UART_SFR_DATA, ESFR_DATA);

  output [7:0]  SFR_DATA;
  output [4:0]  SFR_WRITE_EN;

  input  [6:0]  SOURCE_ADDR, DESTIN_ADDR;
  input         SFR_WRITE;
  input  [7:0]  PSW, ACC, B, PCON, STACK_POINTER;
  input  [7:0]  DPTR_SFR_DATA;
  input  [7:0]  INTR_SFR_DATA;
  input  [7:0]  PORTS_SFR_DATA;
  input  [7:0]  TIMER_SFR_DATA;
  input  [7:0]  UART_SFR_DATA;
  input  [7:0]  ESFR_DATA;

  reg    [7:0]  CORE_SFR_DATA;
  reg    [4:0]  SFR_WRITE_EN;

  // Fixed core SFRs data multiplexer

  always @(STACK_POINTER or PSW or ACC or B or PCON or SOURCE_ADDR)
  begin: p_sfr_mux
    case(SOURCE_ADDR)
      `AddrACC:  CORE_SFR_DATA <= ACC;
      `AddrB:    CORE_SFR_DATA <= B;
      `AddrPSW:  CORE_SFR_DATA <= PSW;
      `AddrSP:   CORE_SFR_DATA <= STACK_POINTER;
      `AddrPCON: CORE_SFR_DATA <= PCON;
      default:   CORE_SFR_DATA <= 8'h00;
    endcase
  end

  // Superimpose the possible sources of SFR data
  assign SFR_DATA = CORE_SFR_DATA | DPTR_SFR_DATA | PORTS_SFR_DATA |
                    INTR_SFR_DATA | TIMER_SFR_DATA | UART_SFR_DATA |
                    ESFR_DATA;

  // Fixed Core SFR Write strobe generator
  always @(DESTIN_ADDR or SFR_WRITE)
  begin: p_sfr_strobes
    if (SFR_WRITE)
      case(DESTIN_ADDR)
        `AddrACC:  SFR_WRITE_EN <= 5'b00001;  // Stack Pointer
        `AddrB:    SFR_WRITE_EN <= 5'b00010;  // PSW
        `AddrPSW:  SFR_WRITE_EN <= 5'b00100;  // Accumulator
        `AddrSP:   SFR_WRITE_EN <= 5'b01000;  // B register
        `AddrPCON: SFR_WRITE_EN <= 5'b10000;  // PCON
        default:   SFR_WRITE_EN <= 5'b00000;
      endcase
    else
      SFR_WRITE_EN <= 5'b00000;
  end

  endmodule
